Conventional memory controllers schedule future memory commands into a pipeline. Some memory specifications, such as for double data rate (DDR) synchronous dynamic random access memory (SDRAM), define foreknown deterministic latencies for scheduling memory commands. For SDRAM, deterministic read latencies enable the memory controller to predict when requested data will be available after a memory core sensing operation.
As the size of memory cells continues to shrink, more phenomena of physics may hinder read operation quality and reliability. Some memory products may include internal mechanisms to quickly correct a small number of bit errors. In such products, the delay of the error-correction may be included in the deterministic read latency applicable to every memory core sensing operation, even those sensing operations which do not require error-correction for a particular iteration.
In the future, a larger percentage of read operations may require error-correction. Deterministic latency requirements often may be satisfied even when performing error-correction, such as for single-bit errors. However, complex error-correction operations may require a longer sensing delay. There is a need, therefore, for memory systems and techniques to provide non-deterministic latency.